Ma ima da ga pretvorimo u srbendu, prvo da nauči da psuje, da razume kada mu se **** pip*** *pip pip *** piip** po spisku kada odgovori tako na ta pitanja i da sledeći put to ne radi ...
Bar tom sokoćalu mogu sve po spisku jer u suprotnom mož da sledi Daisyyyyy ...
Za tehniku je ipak malo bolji ...
>>> hello world example in vhdl
Here is a simple "Hello, World!" example in VHDL:
Bar tom sokoćalu mogu sve po spisku jer u suprotnom mož da sledi Daisyyyyy ...
Za tehniku je ipak malo bolji ...
>>> hello world example in vhdl
Here is a simple "Hello, World!" example in VHDL:
Code:
-- VHDL "Hello, World!" example
library ieee;
use ieee.std_logic_1164.all;
entity hello_world is
port(
clk : in std_logic; -- Clock input
rst : in std_logic; -- Reset input
led : out std_logic -- LED output
);
end entity;
architecture rtl of hello_world is
-- State register
type state_t is (IDLE, HELLO, WORLD, DONE);
signal state : state_t := IDLE;
-- Counter
signal cnt : integer range 0 to 100 := 0;
begin
-- State machine
process(clk, rst)
begin
if (rst = '1') then
state <= IDLE;
cnt <= 0;
led <= '0';
elsif (clk'event and clk = '1') then
case state is
when IDLE =>
if (cnt = 0) then
state <= HELLO;
cnt <= 100;
else
cnt <= cnt - 1;
end if;
when HELLO =>
if (cnt = 0) then
state <= WORLD;
cnt <= 100;
led <= '1';
else
cnt <= cnt - 1;
end if;
when WORLD =>
if (cnt = 0) then
state <= DONE;
cnt <= 100;
led <= '0';
else
cnt <= cnt - 1;
end if;
when DONE =>
if (cnt = 0) then
state <= IDLE;
cnt <= 100;
else
cnt <= cnt - 1;
end if;
end case;
end if;
end process;
end architecture;